深解mos管(guan)驱(qu)(qu)动(dong)电路设计及mos管(guan)驱(qu)(qu)动(dong)电阻(zu)如何选择-KIA MOS管(guan)
信息来源：本站 日期：2019-01-02
跟双极性(xing)晶体(ti)管相比(bi)，一(yi)般认为(wei)使MOS管导通不(bu)需要(yao)(yao)电流，只要(yao)(yao)GS电压高于一(yi)定的值，就可以了。这个很容易做到，但是，我们还需要(yao)(yao)速度。
在(zai)MOS管的(de)结构中可以看到，在(zai)GS，GD之间(jian)存在(zai)寄生(sheng)电(dian)(dian)容(rong)，而MOS管的(de)驱(qu)动(dong)，实(shi)际上(shang)就是对电(dian)(dian)容(rong)的(de)充(chong)放电(dian)(dian)。对电(dian)(dian)容(rong)的(de)充(chong)电(dian)(dian)需要(yao)一个电(dian)(dian)流(liu)，因为对电(dian)(dian)容(rong)充(chong)电(dian)(dian)瞬(shun)(shun)间(jian)可以把电(dian)(dian)容(rong)看成(cheng)短(duan)路，所以瞬(shun)(shun)间(jian)电(dian)(dian)流(liu)会比较大。选择/设计MOS管驱(qu)动(dong)时(shi)第一要(yao)注意的(de)是可提供(gong)瞬(shun)(shun)间(jian)短(duan)路电(dian)(dian)流(liu)的(de)大小。
第二注意(yi)的(de)(de)是(shi)(shi)，普遍用于高(gao)端驱动的(de)(de)NMOS，导通时需(xu)要(yao)是(shi)(shi)栅极(ji)(ji)电(dian)(dian)压(ya)大于源极(ji)(ji)电(dian)(dian)压(ya)。而高(gao)端驱动的(de)(de)MOS管导通时源极(ji)(ji)电(dian)(dian)压(ya)与漏极(ji)(ji)电(dian)(dian)压(ya)（VCC）相同(tong)，所以(yi)这时 栅极(ji)(ji)电(dian)(dian)压(ya)要(yao)比VCC大4V或10V。如果在同(tong)一个系统(tong)里(li)，要(yao)得到比VCC大的(de)(de)电(dian)(dian)压(ya)，就要(yao)专(zhuan)门(men)的(de)(de)升压(ya)电(dian)(dian)路(lu)(lu)了。很多马达驱动器(qi)都集成了电(dian)(dian)荷泵(beng)，要(yao)注意(yi)的(de)(de)是(shi)(shi)应(ying)该 选择合适的(de)(de)外接电(dian)(dian)容，以(yi)得到足(zu)够的(de)(de)短路(lu)(lu)电(dian)(dian)流去驱动MOS管。
上边说的(de)4V或(huo)10V是常用的(de)MOS管(guan)的(de)导(dao)通(tong)电(dian)(dian)压，设计时当然(ran)需要有(you)一定的(de)余量(liang)。而且电(dian)(dian)压越(yue)高，导(dao)通(tong)速度越(yue)快，导(dao)通(tong)电(dian)(dian)阻也越(yue)小。现在也有(you)导(dao)通(tong)电(dian)(dian)压更小的(de)MOS管(guan)用在不同的(de)领域里，但在12V汽(qi)车电(dian)(dian)子(zi)系(xi)统(tong)里，一般4V导(dao)通(tong)就够用了。
MOS管的驱动(dong)电(dian)路及其损失，可以(yi)参考Microchip公司的AN799 Matching MOSFET Drivers to MOSFETs。讲述得很详(xiang)细(xi)，所以(yi)不打(da)算(suan)多写了。
MOS管最显著(zhu)的(de)特(te)性(xing)是开(kai)关(guan)特(te)性(xing)好，所以被(bei)广(guang)泛应(ying)用在需要电子开(kai)关(guan)的(de)电路中，常见的(de)如开(kai)关(guan)电源(yuan)和马(ma)达驱(qu)动，也有照明(ming)调光。
当使用5V电源，这(zhei)(zhei)时(shi)候(hou)(hou)如果(guo)使用传统(tong)的(de)图腾(teng)柱结构，由(you)于三极管的(de)be有0.7V左右的(de)压(ya)降，导致实际最终(zhong)加在gate上的(de)电压(ya)只有4.3V。这(zhei)(zhei)时(shi)候(hou)(hou)，我们(men)选用标称gate电压(ya)4.5V的(de)MOS管就存在一(yi)定的(de)风(feng)险
同样的(de)问(wen)题也发生在(zai)使用3V或者其(qi)他低压电源的(de)场合。
输入电(dian)压并不是一个固定值，它会随着时(shi)间或者其他因素而变动。这个变动导致(zhi)PWM电(dian)路(lu)提供给MOS管的(de)(de)驱(qu)动电(dian)压是不稳定的(de)(de)。
为了让MOS管在(zai)(zai)高gate电压下(xia)安全，很(hen)多MOS管内(nei)置了稳压管强行限制(zhi)gate电压的(de)(de)(de)幅值。在(zai)(zai)这(zhei)种情况下(xia)，当提供的(de)(de)(de)驱动电压超(chao)过稳压管的(de)(de)(de)电压，就会(hui)引(yin)起较大的(de)(de)(de)静态功(gong)耗。
同(tong)时(shi)，如果简单的(de)用电(dian)阻分压(ya)(ya)的(de)原(yuan)理降低gate电(dian)压(ya)(ya)，就会出(chu)现输(shu)入电(dian)压(ya)(ya)比较高的(de)时(shi)候，MOS管工作良好，而输(shu)入电(dian)压(ya)(ya)降低的(de)时(shi)候gate电(dian)压(ya)(ya)不足，引起导(dao)通(tong)不够彻底(di)，从(cong)而增(zeng)加功耗(hao)。
在一些控制(zhi)电(dian)路(lu)中，逻辑部(bu)分(fen)使用典型的(de)5V或者3.3V数(shu)字(zi)电(dian)压(ya)，而(er)功(gong)率部(bu)分(fen)使用12V甚至更高(gao)的(de)电(dian)压(ya)。两个电(dian)压(ya)采用共地(di)方式连(lian)接(jie)。
这就提出一个要求，需要使用一个电路，让(rang)低压(ya)侧(ce)能够有(you)效的(de)控制高压(ya)侧(ce)的(de)MOS管，同时高压(ya)侧(ce)的(de)MOS管也同样(yang)会(hui)面对(dui)1和2中提到的(de)问(wen)题。
在这三种情况下，图腾柱结(jie)构(gou)无法满足输出(chu)要求(qiu)，而(er)很多现成的MOS驱动IC，似乎也没(mei)有包含gate电压(ya)限制(zhi)的结(jie)构(gou)。
电路图如下：
这里只(zhi)针(zhen)对NMOS驱动(dong)电路做一个简单分析：
Vl和Vh分(fen)别是低端(duan)和高端(duan)的电(dian)源(yuan)，两个电(dian)压可以是相同(tong)的，但(dan)是Vl不应该(gai)超过Vh。
Q1和(he)Q2组成了一个反置的图腾(teng)柱(zhu)，用(yong)来(lai)实现(xian)隔离，同时确(que)保两只驱(qu)动管Q3和(he)Q4不会同时导通(tong)。
R2和(he)R3提供(gong)了PWM电压基(ji)准，通过改变这(zhei)个基(ji)准，可以让电路工(gong)作在PWM信号波形比(bi)较(jiao)陡直的(de)位置(zhi)。
Q3和(he)Q4用来提供(gong)驱(qu)动电流(liu)，由(you)于导通(tong)的(de)时候，Q3和(he)Q4相对Vh和(he)GND最低都只有一个Vce的(de)压(ya)降(jiang)，这个压(ya)降(jiang)通(tong)常只有0.3V左(zuo)右，大(da)大(da)低于0.7V的(de)Vce。
R5和(he)R6是反(fan)(fan)馈电(dian)阻，用于对gate电(dian)压进行采(cai)样，采(cai)样后(hou)的电(dian)压通(tong)过(guo)Q5对Q1和(he)Q2的基(ji)极产生一个强烈(lie)的负反(fan)(fan)馈，从而把(ba)gate电(dian)压限(xian)制在一个有限(xian)的数值。这个数值可以通(tong)过(guo)R5和(he)R6来调节(jie)。
最(zui)后，R1提(ti)供了(le)(le)对Q3和(he)Q4的(de)基极电流限(xian)制(zhi)，R4提(ti)供了(le)(le)对MOS管(guan)的(de)gate电流限(xian)制(zhi)，也就是Q3和(he)Q4的(de)Ice的(de)限(xian)制(zhi)。必要的(de)时候可以在R4上面(mian)并联(lian)加速电容(rong)。
这个电路提供了如下的特性：
1，用低端电压和PWM驱动高端MOS管(guan)。
2，用小幅度的PWM信号驱动(dong)高gate电压需求的MOS管。
3，gate电压(ya)的峰值限制
4，输(shu)入和输(shu)出的电流(liu)限制
5，通过使用(yong)合适的电(dian)阻，可(ke)以达到很低的功(gong)耗。
6，PWM信号反(fan)相(xiang)。NMOS并不(bu)需要这个特性，可以通(tong)过前置一(yi)个反(fan)相(xiang)器来解决。
在(zai)设(she)计(ji)(ji)便携式(shi)(shi)设(she)备和无线产品时(shi)，提(ti)高产品性能(neng)、延长(zhang)电池工(gong)作(zuo)时(shi)间是设(she)计(ji)(ji)人员(yuan)需要面对(dui)的两个(ge)问(wen)题。DC-DC转换器具有效(xiao)率高、输(shu)出电流大(da)、静态(tai)电流小(xiao)等优(you)点，非(fei)常适用于为便携式(shi)(shi)设(she)备供电。目前(qian)DC-DC转换器设(she)计(ji)(ji)技术发展主要趋势有：
（1）高频化(hua)技(ji)术：随着开关(guan)频率的(de)(de)提高，开关(guan)变换器的(de)(de)体积也随之减小，功(gong)率密(mi)度(du)也得到大(da)幅提升(sheng)，动(dong)态响应得到改善(shan)。小功(gong)率DC-DC转换器的(de)(de)开关(guan)频率将上(shang)升(sheng)到兆赫级。
（2）低(di)(di)输出电(dian)(dian)压技术：随着半导体制(zhi)造技术的不断发展，微(wei)处(chu)理(li)器和便携(xie)(xie)式电(dian)(dian)子设(she)备的工作(zuo)电(dian)(dian)压越(yue)来越(yue)低(di)(di)，这就要(yao)求(qiu)未来的DC-DC变换器能够提(ti)供低(di)(di)输出电(dian)(dian)压以适应微(wei)处(chu)理(li)器和便携(xie)(xie)式电(dian)(dian)子设(she)备的要(yao)求(qiu)。
这(zhei)些技(ji)术(shu)的(de)(de)(de)发展(zhan)对电(dian)源(yuan)芯片电(dian)路的(de)(de)(de)设计提出了更高的(de)(de)(de)要求。首(shou)先，随着开(kai)(kai)关(guan)频率的(de)(de)(de)不断提高，对于(yu)开(kai)(kai)关(guan)元(yuan)(yuan)件(jian)的(de)(de)(de)性能提出了很高的(de)(de)(de)要求，同时必须具(ju)有相应的(de)(de)(de)开(kai)(kai)关(guan)元(yuan)(yuan)件(jian) 驱动电(dian)路以保证(zheng)开(kai)(kai)关(guan)元(yuan)(yuan)件(jian)在高达兆赫(he)级的(de)(de)(de)开(kai)(kai)关(guan)频率下正常工作(zuo)。其次，对于(yu)电(dian)池(chi)(chi)供(gong)电(dian)的(de)(de)(de)便携式电(dian)子设备来说，电(dian)路的(de)(de)(de)工作(zuo)电(dian)压(ya)低（以锂(li)电(dian)池(chi)(chi)为例，工作(zuo)电(dian)压(ya) 2.5～3.6V），因此，电(dian)源(yuan)芯片的(de)(de)(de)工作(zuo)电(dian)压(ya)较(jiao)低。
MOS管(guan)具有很低的(de)导通电(dian)阻，消耗能(neng)量较低，在目(mu)前流行的(de)高效DC－DC芯片(pian)中多采用MOS管(guan)作为功率(lv)开关(guan)。但是由于MOS管(guan)的(de)寄生(sheng)电(dian)容(rong)大，一(yi)般情(qing)况(kuang)下NMOS开关(guan)管(guan)的(de)栅极电(dian)容(rong)高达(da)几十皮(pi)法。这对于设(she)计高工作频(pin)率(lv)DC－DC转换器开关(guan)管(guan)驱动电(dian)路(lu)的(de)设(she)计提出了更高的(de)要求。
在低(di)电(dian)(dian)压(ya)ULSI设(she)(she)计中有多种(zhong)CMOS、BiCMOS采用(yong)(yong)自(zi)(zi)举(ju)升(sheng)压(ya)结(jie)构的逻辑电(dian)(dian)路(lu)和(he)作为大容性负(fu)载(zai)(zai)(zai)的驱动电(dian)(dian)路(lu)。这些(xie)电(dian)(dian)路(lu)能够在低(di)于(yu)1V电(dian)(dian)压(ya)供(gong)电(dian)(dian)条件下正(zheng)常 工(gong)(gong)(gong)作，并(bing)且能够在负(fu)载(zai)(zai)(zai)电(dian)(dian)容1～2pF的条件下工(gong)(gong)(gong)作频率能够达到几十(shi)兆甚(shen)至(zhi)上百兆赫兹。本(ben)文正(zheng)是采用(yong)(yong)了自(zi)(zi)举(ju)升(sheng)压(ya)电(dian)(dian)路(lu)，设(she)(she)计了一种(zhong)具有大负(fu)载(zai)(zai)(zai)电(dian)(dian)容驱动能力的， 适合于(yu)低(di)电(dian)(dian)压(ya)、高开关频率升(sheng)压(ya)型DC－DC转(zhuan)换器的驱动电(dian)(dian)路(lu)。电(dian)(dian)路(lu)基于(yu)Samsung AHP615 BiCMOS工(gong)(gong)(gong)艺(yi)设(she)(she)计并(bing)经过Hspice仿真验证(zheng)，在供(gong)电(dian)(dian)电(dian)(dian)压(ya)1.5V ，负(fu)载(zai)(zai)(zai)电(dian)(dian)容为60pF时，工(gong)(gong)(gong)作频率能够达到5MHz以上。
MOS管驱(qu)动电(dian)(dian)(dian)(dian)(dian)阻怎么(me)选择(ze),给定(ding)频率,MOS管的(de)(de)(de)(de)Qg和(he)上升(sheng)沿怎么(me)计算用(yong)多大(da)(da)电(dian)(dian)(dian)(dian)(dian)阻首先得知(zhi)道(dao)输入电(dian)(dian)(dian)(dian)(dian)容(rong)大(da)(da)小和(he)驱(qu)动电(dian)(dian)(dian)(dian)(dian)压大(da)(da)小,等效(xiao)为电(dian)(dian)(dian)(dian)(dian)阻和(he)电(dian)(dian)(dian)(dian)(dian)容(rong)串(chuan)联电(dian)(dian)(dian)(dian)(dian)路,求出(chu)电(dian)(dian)(dian)(dian)(dian)容(rong)充电(dian)(dian)(dian)(dian)(dian)电(dian)(dian)(dian)(dian)(dian)压表达式,得出(chu)电(dian)(dian)(dian)(dian)(dian)阻和(he)电(dian)(dian)(dian)(dian)(dian)容(rong)电(dian)(dian)(dian)(dian)(dian)压关(guan)系图MOS管的(de)(de)(de)(de)开关(guan)时间要考虑的(de)(de)(de)(de)是Qg的(de)(de)(de)(de),而(er)不是有Ciss,Coss决定(ding),看(kan)下面的(de)(de)(de)(de)Data.一(yi)个MOS可(ke)能有很(hen)大(da)(da)的(de)(de)(de)(de)输入电(dian)(dian)(dian)(dian)(dian)容(rong),但是并不代表其导通需要的(de)(de)(de)(de)电(dian)(dian)(dian)(dian)(dian)荷量Qg就大(da)(da),Ciss(输入电(dian)(dian)(dian)(dian)(dian)容(rong))和(he)Qg是有一(yi)定(ding)的(de)(de)(de)(de)关(guan)系,但是还(hai)要考虑MOS的(de)(de)(de)(de)跨(kua)导y.
1 、概述
MOS管的(de)驱动(dong)(dong)对(dui)其工作效(xiao)果起着(zhe)决(jue)定性的(de)作用。设(she)计(ji)(ji)师(shi)既要考(kao)虑减少开(kai)关损耗，又要求驱动(dong)(dong)波形(xing)(xing)较好即(ji)振荡小(xiao)、过(guo)冲小(xiao)、EMI小(xiao)。这两方面(mian)往(wang)往(wang)是互相矛盾的(de)，需要寻求一个平衡点(dian)，即(ji)驱动(dong)(dong)电(dian)(dian)路的(de)优化设(she)计(ji)(ji)。驱动(dong)(dong)电(dian)(dian)路的(de)优化设(she)计(ji)(ji)包(bao)含两部(bu)分(fen)内容：一是最(zui)优的(de)驱动(dong)(dong)电(dian)(dian)流(liu)、电(dian)(dian)压的(de)波形(xing)(xing)；二是最(zui)优的(de)驱动(dong)(dong)电(dian)(dian)压、电(dian)(dian)流(liu)的(de)大小(xiao)。在(zai)进(jin)行驱动(dong)(dong)电(dian)(dian)路优化设(she)计(ji)(ji)之前，必须先清楚MOS管的(de)模型(xing)、MOS管的(de)开(kai)关过(guo)程(cheng)、MOS管的(de)栅极电(dian)(dian)荷以及MOS管的(de)输(shu)入(ru)输(shu)出(chu)电(dian)(dian)容、跨接电(dian)(dian)容、等效(xiao)电(dian)(dian)容等参(can)数对(dui)驱动(dong)(dong)的(de)影响(xiang)。
MOS管的等效电路模型及寄生参数如图1所示。图1中各部(bu)分的物理意义为：
（1）LG和LG代表封装端到(dao)实际的(de)栅(zha)极线路(lu)的(de)电(dian)感和电(dian)阻。
（2）C1代表从栅极到源端N+间的电(dian)容，它(ta)的值是由结构所固定(ding)的。
（3）C2+C4代(dai)表(biao)从栅极(ji)到(dao)源极(ji)P区(qu)(qu)间的电(dian)(dian)(dian)容。C2是电(dian)(dian)(dian)介质电(dian)(dian)(dian)容，共值是固定的。而C4是由(you)源极(ji)到(dao)漏极(ji)的耗尽区(qu)(qu)的大(da)小决定，并(bing)随(sui)栅极(ji)电(dian)(dian)(dian)压的大(da)小而改变。当栅极(ji)电(dian)(dian)(dian)压从0升到(dao)开启电(dian)(dian)(dian)压UGS（th）时，C4使整个(ge)栅源电(dian)(dian)(dian)容增加10%～15%。
（4）C3+C5是由一个固(gu)定(ding)大(da)小的电介(jie)质电容(rong)和(he)一个可(ke)变电容(rong)构(gou)成，当漏极电压改变极性时(shi)，其可(ke)变电容(rong)值变得相当大(da)。
（5）C6是随漏极电压变换(huan)的漏源电容。
MOS管输(shu)入电(dian)(dian)容(rong)（Ciss）、跨接电(dian)(dian)容(rong)（Crss）、输(shu)出电(dian)(dian)容(rong)（Coss）和栅源(yuan)电(dian)(dian)容(rong)、栅漏电(dian)(dian)容(rong)、漏源(yuan)电(dian)(dian)容(rong)间(jian)的关系如下(xia)：
开(kai)(kai)(kai)关(guan)管(guan)(guan)(guan)(guan)的(de)(de)(de)(de)(de)(de)开(kai)(kai)(kai)关(guan)模式电(dian)(dian)(dian)(dian)路如(ru)图2所(suo)示，二(er)(er)(er)极(ji)(ji)管(guan)(guan)(guan)(guan)可是外接的(de)(de)(de)(de)(de)(de)或MOS管(guan)(guan)(guan)(guan)固(gu)有的(de)(de)(de)(de)(de)(de)。开(kai)(kai)(kai)关(guan)管(guan)(guan)(guan)(guan)在(zai)(zai)开(kai)(kai)(kai)通(tong)时的(de)(de)(de)(de)(de)(de)二(er)(er)(er)极(ji)(ji)管(guan)(guan)(guan)(guan)电(dian)(dian)(dian)(dian)压、电(dian)(dian)(dian)(dian)流(liu)波形如(ru)图3所(suo)示。在(zai)(zai)图3的(de)(de)(de)(de)(de)(de)阶(jie)(jie)(jie)段1开(kai)(kai)(kai)关(guan)管(guan)(guan)(guan)(guan)关(guan)断，开(kai)(kai)(kai)关(guan)电(dian)(dian)(dian)(dian)流(liu)为(wei)零，此时二(er)(er)(er)极(ji)(ji)管(guan)(guan)(guan)(guan)电(dian)(dian)(dian)(dian)流(liu)和电(dian)(dian)(dian)(dian)感电(dian)(dian)(dian)(dian)流(liu)相等(deng)；在(zai)(zai)阶(jie)(jie)(jie)段2开(kai)(kai)(kai)关(guan)导(dao)通(tong)，开(kai)(kai)(kai)关(guan)电(dian)(dian)(dian)(dian)流(liu)上升，同时二(er)(er)(er)极(ji)(ji)管(guan)(guan)(guan)(guan)电(dian)(dian)(dian)(dian)流(liu)下(xia)(xia)降。开(kai)(kai)(kai)关(guan)电(dian)(dian)(dian)(dian)流(liu)上升的(de)(de)(de)(de)(de)(de)斜(xie)率和二(er)(er)(er)极(ji)(ji)管(guan)(guan)(guan)(guan)电(dian)(dian)(dian)(dian)流(liu)下(xia)(xia)降的(de)(de)(de)(de)(de)(de)斜(xie)率的(de)(de)(de)(de)(de)(de)绝对值(zhi)相同，符(fu)号相反(fan)(fan)；在(zai)(zai)阶(jie)(jie)(jie)段3开(kai)(kai)(kai)关(guan)电(dian)(dian)(dian)(dian)流(liu)继续上升，二(er)(er)(er)极(ji)(ji)管(guan)(guan)(guan)(guan)电(dian)(dian)(dian)(dian)流(liu)继续下(xia)(xia)降，并且二(er)(er)(er)极(ji)(ji)管(guan)(guan)(guan)(guan)电(dian)(dian)(dian)(dian)流(liu)符(fu)号改变，由正转到负；在(zai)(zai)阶(jie)(jie)(jie)段4，二(er)(er)(er)极(ji)(ji)管(guan)(guan)(guan)(guan)从负的(de)(de)(de)(de)(de)(de)反(fan)(fan)向最大电(dian)(dian)(dian)(dian)流(liu)IRRM开(kai)(kai)(kai)始减(jian)小(xiao)，它们斜(xie)率的(de)(de)(de)(de)(de)(de)绝对值(zhi)相等(deng)；在(zai)(zai)阶(jie)(jie)(jie)段5开(kai)(kai)(kai)关(guan)管(guan)(guan)(guan)(guan)完全开(kai)(kai)(kai)通(tong)，二(er)(er)(er)极(ji)(ji)管(guan)(guan)(guan)(guan)的(de)(de)(de)(de)(de)(de)反(fan)(fan)向恢(hui)复(fu)完成，开(kai)(kai)(kai)关(guan)管(guan)(guan)(guan)(guan)电(dian)(dian)(dian)(dian)流(liu)等(deng)于电(dian)(dian)(dian)(dian)感电(dian)(dian)(dian)(dian)流(liu)。
图4是存(cun)储(chu)(chu)电(dian)(dian)荷高或(huo)低(di)的两种二极管电(dian)(dian)流(liu)、电(dian)(dian)压(ya)波形。从图中可(ke)(ke)以看出存(cun)储(chu)(chu)电(dian)(dian)荷少时(shi)，反向电(dian)(dian)压(ya)的斜率大，并且会产生有害的振动。而(er)前(qian)置电(dian)(dian)流(liu)低(di)则存(cun)储(chu)(chu)电(dian)(dian)荷少，即在空(kong)载或(huo)轻载时(shi)是最坏(huai)条件。所以进行(xing)优化驱动电(dian)(dian)路设(she)计时(shi)应(ying)着重考虑前(qian)置电(dian)(dian)流(liu)低(di)的情(qing)况，即空(kong)载或(huo)轻载的情(qing)况，应(ying)使这时(shi)二极管产生的振动在可(ke)(ke)接受范围内(nei)。
栅极(ji)电(dian)(dian)(dian)荷QG是使栅极(ji)电(dian)(dian)(dian)压从0升到(dao)(dao)10V所需的(de)栅极(ji)电(dian)(dian)(dian)荷，它可以表示为驱动电(dian)(dian)(dian)流值(zhi)与(yu)(yu)开通时间之(zhi)(zhi)积或栅极(ji)电(dian)(dian)(dian)容值(zhi)与(yu)(yu)栅极(ji)电(dian)(dian)(dian)压之(zhi)(zhi)积。现在大部分MOS管的(de)栅极(ji)电(dian)(dian)(dian)荷QG值(zhi)从几(ji)十纳库仑(lun)(lun)到(dao)(dao)一、两(liang)百纳库仑(lun)(lun)。
栅极(ji)(ji)(ji)(ji)电(dian)(dian)(dian)荷QG包(bao)含了两个(ge)部(bu)分：栅极(ji)(ji)(ji)(ji)到(dao)(dao)(dao)源极(ji)(ji)(ji)(ji)电(dian)(dian)(dian)荷QGS；栅极(ji)(ji)(ji)(ji)到(dao)(dao)(dao)漏(lou)极(ji)(ji)(ji)(ji)电(dian)(dian)(dian)荷QGD—即“Miller”电(dian)(dian)(dian)荷。QGS是(shi)(shi)(shi)使栅极(ji)(ji)(ji)(ji)电(dian)(dian)(dian)压从(cong)0升到(dao)(dao)(dao)门限值（约3V）所需(xu)电(dian)(dian)(dian)荷；QGD是(shi)(shi)(shi)漏(lou)极(ji)(ji)(ji)(ji)电(dian)(dian)(dian)压下(xia)降时克服“Miller”效(xiao)应(ying)所需(xu)电(dian)(dian)(dian)荷，这(zhei)存在于(yu)UGS曲(qu)线比(bi)较(jiao)平坦的(de)第二(er)段（如图5所示(shi)），此时栅极(ji)(ji)(ji)(ji)电(dian)(dian)(dian)压不变、栅极(ji)(ji)(ji)(ji)电(dian)(dian)(dian)荷积(ji)聚而漏(lou)极(ji)(ji)(ji)(ji)电(dian)(dian)(dian)压急聚下(xia)降，也(ye)就是(shi)(shi)(shi)在这(zhei)时候需(xu)要(yao)驱动尖(jian)峰电(dian)(dian)(dian)流限制(zhi)，这(zhei)由芯(xin)睡内部(bu)完(wan)成(cheng)或外接电(dian)(dian)(dian)阻(zu)完(wan)成(cheng)。实(shi)际的(de)QG还可(ke)以略大，以减(jian)小(xiao)等效(xiao)RON，但是(shi)(shi)(shi)太(tai)大也(ye)无益，所以10V到(dao)(dao)(dao)12V的(de)驱动电(dian)(dian)(dian)压是(shi)(shi)(shi)比(bi)较(jiao)合理(li)的(de)。这(zhei)还包(bao)含一个(ge)重要(yao)的(de)事(shi)实(shi)：需(xu)要(yao)一个(ge)高的(de)尖(jian)峰电(dian)(dian)(dian)流以减(jian)小(xiao)MOS管损耗和(he)转换时间(jian)。
重要是的对于IC来说，MOS管的平均电容负荷并不是MOS管的输入电容Ciss,而是等效输入电容Ceff(Ceff=QG/UGS)，即整个0
漏极(ji)电(dian)流在QG波(bo)形的QGD阶段出现，该(gai)段漏极(ji)电(dian)压(ya)依(yi)然很高(gao)，MOS管(guan)的损(sun)耗该(gai)段最(zui)大，并随UDS的减小而减小。QGD的大部分用来减小UDS从(cong)关(guan)断电(dian)压(ya)到UGS(th)产生的“Miller”效应(ying)。QG波(bo)形第(di)三段的等(deng)效负载电(dian)容(rong)是：
在(zai)大多(duo)数(shu)的开(kai)(kai)关功率(lv)应用电(dian)路中(zhong)(zhong)，当栅极(ji)被驱(qu)(qu)动(dong)，开(kai)(kai)关导通时(shi)漏(lou)极(ji)电(dian)流上(shang)升(sheng)的速(su)(su)度(du)是(shi)漏(lou)极(ji)电(dian)压下(xia)降(jiang)速(su)(su)度(du)的几(ji)倍，这(zhei)将造成功率(lv)损耗增加(jia)。为了解(jie)决问题可以增加(jia)栅极(ji)驱(qu)(qu)动(dong)电(dian)流，但(dan)增加(jia)栅极(ji)驱(qu)(qu)动(dong)上(shang)升(sheng)斜率(lv)又(you)将带来过冲、振荡(dang)、EMI等(deng)问题。优化(hua)栅极(ji)驱(qu)(qu)动(dong)设计，正是(shi)在(zai)互(hu)相矛(mao)盾(dun)的要求中(zhong)(zhong)寻求一(yi)个平衡点(dian)，而(er)这(zhei)个平衡点(dian)就是(shi)开(kai)(kai)关导通时(shi)漏(lou)极(ji)电(dian)流上(shang)升(sheng)的速(su)(su)度(du)和(he)漏(lou)极(ji)电(dian)压下(xia)降(jiang)速(su)(su)度(du)相等(deng)这(zhei)样(yang)一(yi)种波形(xing)，理想的驱(qu)(qu)动(dong)波形(xing)如图6所示(shi)。
图6的(de)(de)UGS波(bo)形包(bao)括了这样(yang)几(ji)部分：UGS第一段(duan)是(shi)快速(su)(su)上(shang)(shang)升(sheng)(sheng)(sheng)(sheng)到(dao)门限电(dian)(dian)(dian)压(ya)；UGS第二段(duan)是(shi)比较(jiao)缓的(de)(de)上(shang)(shang)升(sheng)(sheng)(sheng)(sheng)速(su)(su)度(du)(du)以(yi)减慢漏极(ji)电(dian)(dian)(dian)流(liu)(liu)的(de)(de)上(shang)(shang)升(sheng)(sheng)(sheng)(sheng)速(su)(su)度(du)(du)，但(dan)此(ci)时(shi)(shi)(shi)的(de)(de)UGS也必须(xu)满(man)(man)足所需(xu)的(de)(de)漏极(ji)电(dian)(dian)(dian)流(liu)(liu)值；UGS第四段(duan)快速(su)(su)上(shang)(shang)升(sheng)(sheng)(sheng)(sheng)使漏极(ji)电(dian)(dian)(dian)压(ya)快速(su)(su)下(xia)降；UGS第五段(duan)是(shi)充(chong)电(dian)(dian)(dian)到(dao)最(zui)后的(de)(de)值。当然，要得到(dao)完全一样(yang)的(de)(de)驱动波(bo)形是(shi)很困难的(de)(de)，但(dan)是(shi)可以(yi)得到(dao)一个大(da)(da)概的(de)(de)驱动电(dian)(dian)(dian)流(liu)(liu)波(bo)形，其上(shang)(shang)升(sheng)(sheng)(sheng)(sheng)时(shi)(shi)(shi)间(jian)等于(yu)理想的(de)(de)漏极(ji)电(dian)(dian)(dian)压(ya)下(xia)降时(shi)(shi)(shi)间(jian)或漏极(ji)电(dian)(dian)(dian)流(liu)(liu)上(shang)(shang)升(sheng)(sheng)(sheng)(sheng)的(de)(de)时(shi)(shi)(shi)间(jian)，并且具有足够(gou)的(de)(de)尖(jian)峰(feng)值来(lai)充(chong)电(dian)(dian)(dian)开(kai)关期间(jian)的(de)(de)较(jiao)大(da)(da)等效(xiao)电(dian)(dian)(dian)容(rong)。该栅极(ji)尖(jian)峰(feng)电(dian)(dian)(dian)流(liu)(liu)IP的(de)(de)计算(suan)是(shi)：电(dian)(dian)(dian)荷必须(xu)完全满(man)(man)足开(kai)关时(shi)(shi)(shi)期的(de)(de)寄生电(dian)(dian)(dian)容(rong)所需(xu)。
6 应用实例
在笔者设计的(de)48V50A电(dian)路(lu)中采(cai)用双晶体管正(zheng)激式变换电(dian)路(lu)，其(qi)开关管采(cai)用IXFH24N50，其(qi)参数为：
根据(ju)如(ru)前所述，驱动(dong)电(dian)(dian)压、电(dian)(dian)流的(de)理(li)想(xiang)波形(xing)不应该是一条直线，而应该是如(ru)图6所示的(de)波形(xing)。实(shi)验波形(xing)见图7。
7、结论
本文详(xiang)细介绍了MOS管的电路模型、开关过(guo)程(cheng)、输(shu)入输(shu)出电容、等效(xiao)电容、电荷存储等对MOS管驱动波形(xing)(xing)的影响(xiang)(xiang)，及(ji)根据(ju)这些参数对驱动波形(xing)(xing)的影响(xiang)(xiang)进行的驱动波形(xing)(xing)的优化(hua)设计实(shi)例，取得(de)了较(jiao)好的实(shi)际效(xiao)果。
影响(xiang)MOSFET开(kai)关速度(du)除了其(qi)本身固有(you)Tr,Tf外(wai),还(hai)有(you)一(yi)个重要的参(can)数:Qg (栅(zha)极(ji)总静(jing)电(dian)(dian)(dian)(dian)荷容量(liang)).该参(can)数与栅(zha)极(ji)驱动(dong)电(dian)(dian)(dian)(dian)路的输(shu)出内(nei)(nei)阻共(gong)同构成(cheng)了一(yi)个时间(jian)参(can)数,影响(xiang)着MOSFET的性能(你主板的MOSFET的栅(zha)极(ji)驱动(dong)电(dian)(dian)(dian)(dian)路就集成(cheng)在(zai)(zai)IRU3055这块PWM控制芯(xin)片(pian)内(nei)(nei)); r6 @0 k" S/ l3 }4 u, r/ W厂家给出的Tr,Tf值,是在(zai)(zai)栅(zha)极(ji)驱动(dong)内(nei)(nei)阻小到可以忽略的情况下测出的,实际(ji)应用中就不(bu)一(yi)样了,特(te)别是栅(zha)极(ji)驱动(dong)集成(cheng)在(zai)(zai)PWM芯(xin)片(pian)中的电(dian)(dian)(dian)(dian)路,从(cong)PWM到MOSFET栅(zha)极(ji)的布线的宽度(du),长(zhang)度(du),都(dou)会深刻(ke)影响(xiang)MOSFET的性能.如果PWM的输(shu)出内(nei)(nei)阻本来(lai)就不(bu)低(di),加(jia)上MOS管的Qg又大(da),那(nei)么不(bu)论其(qi)Tr,Tf如何优秀,都(dou)可能会大(da)大(da)增加(jia)上升和下降的时间(jian)
偶认为,BUCK同步(bu)变换器中,高侧(ce)MOS管的(de)Qg比RDS等其他参数更重要,另(ling)外,栅极驱动内(nei)阻与Qg的(de)配合也(ye)很重要,一定 程度(du)上就是由它的(de)充电时(shi)间决定高侧(ce)MOSFET的(de)开关速度(du)和损耗..
看(kan)从哪个(ge)角度(du)出(chu)发。电(dian)(dian)(dian)荷泻放(fang)(fang)慢，说明时(shi)间(jian)(jian)常数(shu)大(da)(da)。时(shi)间(jian)(jian)常数(shu)是Ciss与(yu)(yu)Rgs的乘积。栅(zha)(zha)源极绝缘电(dian)(dian)(dian)阻(zu)大(da)(da)，说明制(zhi)造工艺控(kong)制(zhi)较好，材料、芯(xin)(xin)(xin)片和管(guan)壳(qiao)封装的表面杂(za)质少，漏电(dian)(dian)(dian)少。时(shi)间(jian)(jian)常数(shu)大(da)(da)，栅(zha)(zha)源极等(deng)(deng)效输入电(dian)(dian)(dian)容(rong)也(ye)大(da)(da)。栅(zha)(zha)源极等(deng)(deng)效输入电(dian)(dian)(dian)容(rong)，与(yu)(yu)管(guan)芯(xin)(xin)(xin)尺寸(cun)成正比(bi)并(bing)与(yu)(yu)管(guan)芯(xin)(xin)(xin)设(she)计有(you)关(guan)。通常，管(guan)芯(xin)(xin)(xin)尺寸(cun)大(da)(da)，Ron(导通电(dian)(dian)(dian)阻(zu))小(xiao)、跨(kua)导（增(zeng)益(yi)）大(da)(da)。栅(zha)(zha)源极等(deng)(deng)效电(dian)(dian)(dian)容(rong)大(da)(da)，会增(zeng)加开关(guan)时(shi)间(jian)(jian)、降低开关(guan)性能、降低工作速度(du)、增(zeng)加功率损耗。Ciss与(yu)(yu)电(dian)(dian)(dian)荷注入率成正比(bi)，可能还与(yu)(yu)外加电(dian)(dian)(dian)压有(you)关(guan)并(bing)具有(you)非线性等(deng)(deng)。以上(shang)，均(jun)是在(zai)相同(tong)条件下的对比(bi)。从应(ying)用角度(du)出(chu)发，同(tong)等(deng)(deng)价格，多数(shu)设(she)计希望(wang)选用3个(ge)等(deng)(deng)效电(dian)(dian)(dian)容(rong)（包括Ciss）小(xiao)的器(qi)件。Ciss=Cgd+Cgs，充(chong)放(fang)(fang)电(dian)(dian)(dian)时(shi)间(jian)(jian)上(shang)也(ye)有(you)先后(hou)(hou)，先是Cgs充(chong)满，然后(hou)(hou)是Cgd.。
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