MOS管(guan)，CMOS-MOS管(guan)CMOS集成(cheng)电路(lu)、工作(zuo)原(yuan)理(li)解析以及简单比较-KIA MOS管(guan)
信息来(lai)源：本站 日期：2018-07-19
MOSFET管(guan)(guan)是FET的(de)(de)(de)(de)(de)一(yi)(yi)(yi)种(zhong)（另一(yi)(yi)(yi)种(zhong)是JFET），可(ke)以(yi)被制(zhi)造成(cheng)增强(qiang)型(xing)或耗尽型(xing)，P沟(gou)(gou)道(dao)或N沟(gou)(gou)道(dao)共4种(zhong)类型(xing)，但(dan)(dan)实(shi)际应用的(de)(de)(de)(de)(de)只(zhi)有增强(qiang)型(xing)的(de)(de)(de)(de)(de)N沟(gou)(gou)道(dao)MOS管(guan)(guan)型(xing)号(hao)和(he)增强(qiang)型(xing)的(de)(de)(de)(de)(de)P沟(gou)(gou)道(dao)MOS管(guan)(guan)型(xing)号(hao)，所以(yi)通常提到NMOS，或者PMOS指的(de)(de)(de)(de)(de)就是这两(liang)种(zhong)。至于(yu)为什么不使用耗尽型(xing)的(de)(de)(de)(de)(de)MOS管(guan)(guan)，不建议刨根问底。对于(yu)这两(liang)种(zhong)增强(qiang)型(xing)MOS管(guan)(guan)，比较常用的(de)(de)(de)(de)(de)是NMOS。原因是导通电阻小，且(qie)容(rong)易(yi)制(zhi)造。所以(yi)开关电源(yuan)和(he)马达驱(qu)动的(de)(de)(de)(de)(de)应用中(zhong)，一(yi)(yi)(yi)般都用NMOS。下面的(de)(de)(de)(de)(de)介绍中(zhong)，也(ye)多以(yi)NMOS为主。 MOS管(guan)(guan)的(de)(de)(de)(de)(de)三个(ge)管(guan)(guan)脚之间(jian)有寄生(sheng)电容(rong)存(cun)(cun)在(zai)(zai)(zai)(zai)(zai)，这不是我(wo)们需要的(de)(de)(de)(de)(de)，而是由于(yu)制(zhi)造工艺限制(zhi)产生(sheng)的(de)(de)(de)(de)(de)。寄生(sheng)电容(rong)的(de)(de)(de)(de)(de)存(cun)(cun)在(zai)(zai)(zai)(zai)(zai)使得在(zai)(zai)(zai)(zai)(zai)设计或选择驱(qu)动电路的(de)(de)(de)(de)(de)时候要麻(ma)烦一(yi)(yi)(yi)些，但(dan)(dan)没(mei)有办法避免，后边(bian)再详细介绍。在(zai)(zai)(zai)(zai)(zai)MOS管(guan)(guan)原理图(tu)上可(ke)以(yi)看到，漏(lou)极(ji)和(he)源(yuan)极(ji)之间(jian)有一(yi)(yi)(yi)个(ge)寄生(sheng)二(er)极(ji)管(guan)(guan)。这个(ge)叫(jiao)体二(er)极(ji)管(guan)(guan)，在(zai)(zai)(zai)(zai)(zai)驱(qu)动感性(xing)负载，这个(ge)二(er)极(ji)管(guan)(guan)很重要。顺(shun)便(bian)说(shuo)一(yi)(yi)(yi)句，体二(er)极(ji)管(guan)(guan)只(zhi)在(zai)(zai)(zai)(zai)(zai)单(dan)个(ge)的(de)(de)(de)(de)(de)MOS管(guan)(guan)中(zhong)存(cun)(cun)在(zai)(zai)(zai)(zai)(zai)，在(zai)(zai)(zai)(zai)(zai)集成(cheng)电路芯片内部通常是没(mei)有的(de)(de)(de)(de)(de)。
导(dao)通的(de)(de)(de)意(yi)思是作(zuo)为开(kai)(kai)关(guan)，相(xiang)当于开(kai)(kai)关(guan)闭(bi)合。NMOS的(de)(de)(de)特性，Vgs大(da)于一(yi)定的(de)(de)(de)值(zhi)就(jiu)(jiu)会导(dao)通，适合用(yong)于源(yuan)极接(jie)地(di)时的(de)(de)(de)情况（低(di)端驱(qu)(qu)动(dong)），只要栅极电(dian)压达到(dao)4V或10V就(jiu)(jiu)可以了。PMOS的(de)(de)(de)特性，Vgs小于一(yi)定的(de)(de)(de)值(zhi)就(jiu)(jiu)会导(dao)通，适合用(yong)于源(yuan)极接(jie)VCC时的(de)(de)(de)情况（高端驱(qu)(qu)动(dong)）。但(dan)是，虽然PMOS可以很方便地(di)用(yong)作(zuo)高端驱(qu)(qu)动(dong)，但(dan)由于导(dao)通电(dian)阻大(da)，价格贵，替换种类少等(deng)原因，在高端驱(qu)(qu)动(dong)中，通常(chang)还是使用(yong)NMOS。
不管(guan)是(shi)(shi)NMOS还是(shi)(shi)PMOS，导(dao)通(tong)后都有导(dao)通(tong)电(dian)(dian)(dian)(dian)(dian)阻存(cun)在(zai)，这(zhei)样电(dian)(dian)(dian)(dian)(dian)流(liu)(liu)就会在(zai)这(zhei)个电(dian)(dian)(dian)(dian)(dian)阻上(shang)消耗(hao)能量(liang)，这(zhei)部(bu)分消耗(hao)的(de)(de)(de)能量(liang)叫做(zuo)导(dao)通(tong)损(sun)耗(hao)。选择导(dao)通(tong)电(dian)(dian)(dian)(dian)(dian)阻小(xiao)的(de)(de)(de)MOS管(guan)会减小(xiao)导(dao)通(tong)损(sun)耗(hao)。现(xian)在(zai)的(de)(de)(de)小(xiao)功率(lv)MOS管(guan)导(dao)通(tong)电(dian)(dian)(dian)(dian)(dian)阻一般在(zai)几十毫(hao)欧(ou)左右，几毫(hao)欧(ou)的(de)(de)(de)也(ye)有。MOS在(zai)导(dao)通(tong)和(he)截止的(de)(de)(de)时候，一定不是(shi)(shi)在(zai)瞬(shun)间(jian)(jian)完成的(de)(de)(de)。MOS两(liang)端的(de)(de)(de)电(dian)(dian)(dian)(dian)(dian)压有一个下降(jiang)的(de)(de)(de)过(guo)程，流(liu)(liu)过(guo)的(de)(de)(de)电(dian)(dian)(dian)(dian)(dian)流(liu)(liu)有一个上(shang)升的(de)(de)(de)过(guo)程，在(zai)这(zhei)段时间(jian)(jian)内，MOS管(guan)的(de)(de)(de)损(sun)失(shi)(shi)是(shi)(shi)电(dian)(dian)(dian)(dian)(dian)压和(he)电(dian)(dian)(dian)(dian)(dian)流(liu)(liu)的(de)(de)(de)乘(cheng)积，叫做(zuo)开(kai)关损(sun)失(shi)(shi)。通(tong)常开(kai)关损(sun)失(shi)(shi)比导(dao)通(tong)损(sun)失(shi)(shi)大(da)(da)得多，而且开(kai)关频率(lv)越快，损(sun)失(shi)(shi)也(ye)越大(da)(da)。导(dao)通(tong)瞬(shun)间(jian)(jian)电(dian)(dian)(dian)(dian)(dian)压和(he)电(dian)(dian)(dian)(dian)(dian)流(liu)(liu)的(de)(de)(de)乘(cheng)积很大(da)(da)，造成的(de)(de)(de)损(sun)失(shi)(shi)也(ye)就很大(da)(da)。缩(suo)短开(kai)关时间(jian)(jian)，可以(yi)减小(xiao)每次导(dao)通(tong)时的(de)(de)(de)损(sun)失(shi)(shi)；降(jiang)低开(kai)关频率(lv)，可以(yi)减小(xiao)单(dan)位时间(jian)(jian)内的(de)(de)(de)开(kai)关次数。这(zhei)两(liang)种办法(fa)都可以(yi)减小(xiao)开(kai)关损(sun)失(shi)(shi)。
跟双极性晶体管相比，一般认为(wei)使MOS管导(dao)通(tong)不需要(yao)(yao)电(dian)(dian)(dian)(dian)(dian)(dian)流(liu)，只要(yao)(yao)GS电(dian)(dian)(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)(ya)高于一定的(de)(de)(de)(de)值，就(jiu)可(ke)以了(le)(le)。这(zhei)个(ge)很容(rong)易(yi)做到(dao)(dao)，但是(shi)(shi)，我们还需要(yao)(yao)速度。在(zai)MOS管的(de)(de)(de)(de)结构中可(ke)以看到(dao)(dao)，在(zai)GS，GD之(zhi)间(jian)存(cun)在(zai)寄(ji)生电(dian)(dian)(dian)(dian)(dian)(dian)容(rong)，而(er)MOS管的(de)(de)(de)(de)驱(qu)(qu)动(dong)，实际上就(jiu)是(shi)(shi)对(dui)(dui)电(dian)(dian)(dian)(dian)(dian)(dian)容(rong)的(de)(de)(de)(de)充放电(dian)(dian)(dian)(dian)(dian)(dian)。对(dui)(dui)电(dian)(dian)(dian)(dian)(dian)(dian)容(rong)的(de)(de)(de)(de)充电(dian)(dian)(dian)(dian)(dian)(dian)需要(yao)(yao)一个(ge)电(dian)(dian)(dian)(dian)(dian)(dian)流(liu)，因(yin)为(wei)对(dui)(dui)电(dian)(dian)(dian)(dian)(dian)(dian)容(rong)充电(dian)(dian)(dian)(dian)(dian)(dian)瞬(shun)间(jian)可(ke)以把电(dian)(dian)(dian)(dian)(dian)(dian)容(rong)看成短路(lu)，所以瞬(shun)间(jian)电(dian)(dian)(dian)(dian)(dian)(dian)流(liu)会比较(jiao)大。选择(ze)(ze)/设计MOS管驱(qu)(qu)动(dong)时(shi)(shi)(shi)第(di)一要(yao)(yao)注意(yi)的(de)(de)(de)(de)是(shi)(shi)可(ke)提(ti)供瞬(shun)间(jian)短路(lu)电(dian)(dian)(dian)(dian)(dian)(dian)流(liu)的(de)(de)(de)(de)大小。第(di)二注意(yi)的(de)(de)(de)(de)是(shi)(shi)，普遍用(yong)于高端驱(qu)(qu)动(dong)的(de)(de)(de)(de)NMOS，导(dao)通(tong)时(shi)(shi)(shi)需要(yao)(yao)是(shi)(shi)栅极电(dian)(dian)(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)(ya)大于源极电(dian)(dian)(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)(ya)。而(er)高端驱(qu)(qu)动(dong)的(de)(de)(de)(de)MOS管导(dao)通(tong)时(shi)(shi)(shi)源极电(dian)(dian)(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)(ya)与漏极电(dian)(dian)(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)(ya)（VCC）相同，所以这(zhei)时(shi)(shi)(shi)栅极电(dian)(dian)(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)(ya)要(yao)(yao)比VCC大4V或(huo)10V。如(ru)果在(zai)同一个(ge)系统里(li)，要(yao)(yao)得(de)到(dao)(dao)比VCC大的(de)(de)(de)(de)电(dian)(dian)(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)(ya)，就(jiu)要(yao)(yao)专门(men)的(de)(de)(de)(de)升压(ya)(ya)(ya)(ya)(ya)电(dian)(dian)(dian)(dian)(dian)(dian)路(lu)了(le)(le)。很多马(ma)达驱(qu)(qu)动(dong)器都集(ji)成了(le)(le)电(dian)(dian)(dian)(dian)(dian)(dian)荷(he)泵，要(yao)(yao)注意(yi)的(de)(de)(de)(de)是(shi)(shi)应该选择(ze)(ze)合适的(de)(de)(de)(de)外接(jie)电(dian)(dian)(dian)(dian)(dian)(dian)容(rong)，以得(de)到(dao)(dao)足够(gou)的(de)(de)(de)(de)短路(lu)电(dian)(dian)(dian)(dian)(dian)(dian)流(liu)去(qu)驱(qu)(qu)动(dong)MOS管。上边说的(de)(de)(de)(de)4V或(huo)10V是(shi)(shi)常用(yong)的(de)(de)(de)(de)MOS管的(de)(de)(de)(de)导(dao)通(tong)电(dian)(dian)(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)(ya)，设计时(shi)(shi)(shi)当然需要(yao)(yao)有一定的(de)(de)(de)(de)余量。而(er)且电(dian)(dian)(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)(ya)越高，导(dao)通(tong)速度越快，导(dao)通(tong)电(dian)(dian)(dian)(dian)(dian)(dian)阻也越小。现在(zai)也有导(dao)通(tong)电(dian)(dian)(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)(ya)更(geng)小的(de)(de)(de)(de)MOS管用(yong)在(zai)不同的(de)(de)(de)(de)领域里(li)，但在(zai)12V汽车电(dian)(dian)(dian)(dian)(dian)(dian)子系统里(li)，一般4V导(dao)通(tong)就(jiu)够(gou)用(yong)了(le)(le)。
MOS集(ji)成(cheng)电路特点：制造(zao)工艺比较(jiao)简单(dan)、成(cheng)品率较(jiao)高、功耗低、组成(cheng)的逻辑电路比较(jiao)简单(dan)，集(ji)成(cheng)度高、抗干扰能力强，特别适(shi)合于大规(gui)模集(ji)成(cheng)电路。
MOS集成(cheng)(cheng)电(dian)(dian)路包括(kuo):NMOS管(guan)组成(cheng)(cheng)的NMOS电(dian)(dian)路、PMOS管(guan)组成(cheng)(cheng)的PMOS电(dian)(dian)路及由(you)NMOS和PMOS两(liang)种管(guan)子组成(cheng)(cheng)的互补(bu)MOS电(dian)(dian)路，即CMOS电(dian)(dian)路。
PMOS门电路(lu)与NMOS电路(lu)的原理完全相同，只是电源极(ji)性相反而已。
数(shu)字电(dian)路中MOS集(ji)成(cheng)电(dian)路所使用(yong)的MOS管(guan)均为增强型管(guan)子，负(fu)载常(chang)用(yong)MOS管(guan)作为有源负(fu)载，这样(yang)不仅节(jie)省了硅片面(mian)积(ji)，而且简化了工(gong)艺利于大规模集(ji)成(cheng)。常(chang)用(yong)的符号如图所示。
CMOS是(shi)Complementary Metal Oxide Semiconductor（互补金属氧化物半(ban)导体(ti)）的缩写。它是(shi)指制造(zao)大规(gui)模(mo)集(ji)成电(dian)路芯片(pian)用(yong)(yong)的一种技术或用(yong)(yong)这(zhei)种技术制造(zao)出来(lai)的芯片(pian)，是(shi)电(dian)脑(nao)主板上的一块(kuai)可读写的RAM芯片(pian)。因(yin)为可读写的特性，所以(yi)在电(dian)脑(nao)主板上用(yong)(yong)来(lai)保存(cun)BIOS设(she)置(zhi)完(wan)电(dian)脑(nao)硬件参数(shu)后的数(shu)据，这(zhei)个(ge)芯片(pian)仅(jin)仅(jin)是(shi)用(yong)(yong)来(lai)存(cun)放数(shu)据的。而对BIOS中各项参数(shu)的设(she)定要通过专门(men)的程(cheng)序。BIOS设(she)置(zhi)程(cheng)序一般都被(bei)厂商整合在芯片(pian)中，在开(kai)机时通过特定的按键(jian)就可进(jin)入BIOS设(she)置(zhi)程(cheng)序，方便地(di)对系统进(jin)行设(she)置(zhi)。因(yin)此BIOS设(she)置(zhi)有时也被(bei)叫(jiao)做CMOS设(she)置(zhi)。
（1）功(gong)耗低
CMOS集成电(dian)路采用场(chang)效(xiao)(xiao)应(ying)管(guan)，且都是(shi)互补结(jie)构(gou)，工(gong)作(zuo)时两(liang)个(ge)串联(lian)的场(chang)效(xiao)(xiao)应(ying)管(guan)总是(shi)处于(yu)(yu)一(yi)个(ge)管(guan)导(dao)通，另一(yi)个(ge)管(guan)截(jie)止(zhi)的状(zhuang)态(tai)，电(dian)路静态(tai)功耗理论上为零。实际上，由于(yu)(yu)存在漏电(dian)流，CMOS电(dian)路尚(shang)有微量静态(tai)功耗。单(dan)个(ge)门电(dian)路的功耗典型(xing)值仅为20mW，动(dong)态(tai)功耗（在1MHz工(gong)作(zuo)频(pin)率时）也仅为几mW。
（2）工作电压范围宽
CMOS集(ji)成(cheng)电路供(gong)电简(jian)单(dan)，供(gong)电电源体积小，基(ji)本上不需稳压。国产CC4000系列的(de)集(ji)成(cheng)电路，可在3~18V电压下正常工作。
（3）逻(luo)辑(ji)摆幅大CMOS集成电(dian)路的逻(luo)辑(ji)高(gao)电(dian)平“1”、逻(luo)辑(ji)低电(dian)平“0”分(fen)别(bie)接(jie)近(jin)于电(dian)源高(gao)电(dian)位VDD及电(dian)影低电(dian)位VSS。当(dang)VDD=15V，VSS=0V时，输出逻(luo)辑(ji)摆幅近(jin)似15V。因此，CMOS集成电(dian)路的电(dian)压利用系数在各类集成电(dian)路中指标是较高(gao)的。
（4）抗干扰能力强
CMOS集(ji)成(cheng)电(dian)(dian)路(lu)(lu)的(de)(de)(de)(de)电(dian)(dian)压噪声(sheng)容(rong)限(xian)的(de)(de)(de)(de)典(dian)型值为电(dian)(dian)源(yuan)(yuan)电(dian)(dian)压的(de)(de)(de)(de)45%，保证值为电(dian)(dian)源(yuan)(yuan)电(dian)(dian)压的(de)(de)(de)(de)30%。随着电(dian)(dian)源(yuan)(yuan)电(dian)(dian)压的(de)(de)(de)(de)增(zeng)加，噪声(sheng)容(rong)限(xian)电(dian)(dian)压的(de)(de)(de)(de)绝对值将成(cheng)比(bi)例增(zeng)加。对于VDD=15V的(de)(de)(de)(de)供(gong)电(dian)(dian)电(dian)(dian)压（当VSS=0V时），电(dian)(dian)路(lu)(lu)将有(you)7V左(zuo)右的(de)(de)(de)(de)噪声(sheng)容(rong)限(xian)。
（5）输入阻(zu)抗高(gao)
CMOS集成(cheng)电(dian)(dian)路的(de)输(shu)入(ru)端(duan)一般(ban)都是由保(bao)护(hu)二极管(guan)和串联电(dian)(dian)阻(zu)构成(cheng)的(de)保(bao)护(hu)网络，故(gu)比(bi)一般(ban)场效应(ying)管(guan)的(de)输(shu)入(ru)电(dian)(dian)阻(zu)稍小，但(dan)在(zai)正常(chang)工作(zuo)电(dian)(dian)压范(fan)围内，这些保(bao)护(hu)二极管(guan)均处(chu)于反向偏置状态，直流输(shu)入(ru)阻(zu)抗取(qu)决于这些二极管(guan)的(de)泄露电(dian)(dian)流，通常(chang)情况下，等(deng)效输(shu)入(ru)阻(zu)抗高达103~1011Ω，因此CMOS集成(cheng)电(dian)(dian)路几乎(hu)不消耗驱动电(dian)(dian)路的(de)功率。
（6）温度稳(wen)定性能好
由于CMOS集成电(dian)路(lu)的功耗(hao)很低(di)，内部(bu)发热量少(shao)，而(er)且，CMOS电(dian)路(lu)线路(lu)结构(gou)和电(dian)气参数(shu)都(dou)具(ju)有对称性，在温(wen)度环境发生变化时，某些参数(shu)能起到自动补偿作用，因而(er)CMOS集成电(dian)路(lu)的温(wen)度特性非常好。一(yi)般(ban)陶瓷金属封装的电(dian)路(lu)，工作温(wen)度为(wei)-55 ~ +125℃；塑料封装的电(dian)路(lu)工作温(wen)度范围(wei)为(wei)-45 ~ +85℃。
（7）扇出(chu)能力强
扇出(chu)能力是用电路输(shu)出(chu)端所能带动的(de)(de)输(shu)入(ru)端数来(lai)表示(shi)的(de)(de)。由(you)于CMOS集(ji)(ji)成电路的(de)(de)输(shu)入(ru)阻抗极高，因此电路的(de)(de)输(shu)出(chu)能力受(shou)输(shu)入(ru)电容(rong)的(de)(de)限制，但是，当CMOS集(ji)(ji)成电路用来(lai)驱(qu)(qu)动同类型(xing)，如不(bu)考虑速度，一般可(ke)以驱(qu)(qu)动50个以上(shang)的(de)(de)输(shu)入(ru)端。
（8）抗辐射(she)能力(li)强
CMOS集成电路中的(de)基本器件是MOS晶体管，属于多(duo)数载流子导电器件。各种射(she)线、辐射(she)对其导电性能(neng)的(de)影响都有限，因而特别适用(yong)于制作航天(tian)及核实验设备。
（9）可控性好
CMOS集(ji)成电路(lu)输(shu)出波形的(de)上(shang)升和(he)下降时(shi)间(jian)(jian)可以控制，其(qi)输(shu)出的(de)上(shang)升和(he)下降时(shi)间(jian)(jian)的(de)典型(xing)值为电路(lu)传输(shu)延迟时(shi)间(jian)(jian)的(de)125%~140%。
（10）接口(kou)方便
因为(wei)CMOS集成电(dian)路的输入阻抗(kang)高和输出摆幅大，所以易于被其他电(dian)路所驱(qu)动，也容易驱(qu)动其他类型的电(dian)路或器件。
以CMOS集成(cheng)电(dian)路中的一(yi)个(ge)最基本电(dian)路——反(fan)(fan)相器(qi)（其他(ta)复杂的CMOS集成(cheng)电(dian)路大(da)多是由反(fan)(fan)相器(qi)单元组(zu)合而成(cheng)）为例(li)，分析CMOS集成(cheng)电(dian)路的工作(zuo)过(guo)程。
利用一个P沟(gou)道MOS管和一个N沟(gou)道MOS管互补连接就(jiu)构成(cheng)了一个最基本的反相器单(dan)元电(dian)路(lu)如(ru)附图所示。图2中(zhong)VDD为(wei)(wei)正电(dian)源(yuan)端，VSS为(wei)(wei)负电(dian)源(yuan)端。电(dian)路(lu)设(she)计采用正逻(luo)辑(ji)(ji)方法，即(ji)逻(luo)辑(ji)(ji)“1”为(wei)(wei)高电(dian)平，逻(luo)辑(ji)(ji)“0”为(wei)(wei)低电(dian)平。
图2中，当输(shu)入电(dian)(dian)压(ya)VI为低电(dian)(dian)平“0”（VSS）时，N沟(gou)道(dao)MOS管(guan)(guan)的栅-源(yuan)电(dian)(dian)压(ya)VGSN=0V（源(yuan)极(ji)和衬底一起(qi)接VSS），由于是增(zeng)强型管(guan)(guan)，所以管(guan)(guan)子(zi)截止，而P沟(gou)道(dao)MOS管(guan)(guan)的栅-源(yuan)电(dian)(dian)压(ya)VGSN=VSS—VDD。若|VSS—VDD|>|VTP|（MOS管(guan)(guan)开(kai)启电(dian)(dian)压(ya)），则(ze)P沟(gou)道(dao)MOS管(guan)(guan)导(dao)通，所以输(shu)出电(dian)(dian)压(ya)V0为高电(dian)(dian)平“1”（VDD），实现了输(shu)入和输(shu)出的反相功能。
当输(shu)入电(dian)压VI为底(di)电(dian)平(ping)“1”（VDD）时，VGSN=（VDD—VSS）。若（VDD—VSS）>VGSN，则(ze)N沟道MOS管导通，此时VGSN=0V，P沟道MOS管截止，所以输(shu)出电(dian)压V0为低电(dian)平(ping)“0”（VSS），与VI互为反相关(guan)系。
由上述(shu)分(fen)析可知(zhi)，当输入信号(hao)为“0”或“1”的(de)(de)稳定状(zhuang)态时，电路中的(de)(de)两个MOS管总(zong)有一(yi)个处于截止(zhi)状(zhuang)态，使得VDD和VSS之间无低阻(zu)抗直流通路，因此(ci)静(jing)态功耗极小。这便是CMOS集(ji)成电路最主(zhu)要的(de)(de)特(te)点。
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