PMOS晶体管

金属氧(yang)化物半导(dao)体(ti)(ti)(ti)(ti)场(chang)效(xiao)应(MOS)晶体(ti)(ti)(ti)(ti)管(guan)(guan)可分为N沟(gou)道(dao)(dao)(dao)与P沟(gou)道(dao)(dao)(dao)两大类(lei)，P沟(gou)道(dao)(dao)(dao)硅(gui)MOS场(chang)效(xiao)应晶体(ti)(ti)(ti)(ti)管(guan)(guan)在N型硅(gui)衬底上有(you)两个P+区(qu)，分别(bie)叫做源极(ji)(ji)和(he)漏(lou)极(ji)(ji)，两极(ji)(ji)之间不通导(dao)，柵极(ji)(ji)上加(jia)有(you)足够(gou)的(de)(de)正电(dian)(dian)压(ya)(源极(ji)(ji)接(jie)地)时(shi)，柵极(ji)(ji)下的(de)(de)N型硅(gui)表(biao)面(mian)呈现P型反(fan)型层(ceng)，成(cheng)为连接(jie)源极(ji)(ji)和(he)漏(lou)极(ji)(ji)的(de)(de)沟(gou)道(dao)(dao)(dao)。改变栅(zha)压(ya)可以改变沟(gou)道(dao)(dao)(dao)中的(de)(de)电(dian)(dian)子密度，从而改变沟(gou)道(dao)(dao)(dao)的(de)(de)电(dian)(dian)阻(zu)。这(zhei)种MOS场(chang)效(xiao)应晶体(ti)(ti)(ti)(ti)管(guan)(guan)称(cheng)为P沟(gou)道(dao)(dao)(dao)增(zeng)(zeng)强(qiang)型场(chang)效(xiao)应晶体(ti)(ti)(ti)(ti)管(guan)(guan)。如果N型硅(gui)衬底表(biao)面(mian)不加(jia)栅(zha)压(ya)就已存(cun)在P型反(fan)型层(ceng)沟(gou)道(dao)(dao)(dao)，加(jia)上适当的(de)(de)偏(pian)压(ya)，可使沟(gou)道(dao)(dao)(dao)的(de)(de)电(dian)(dian)阻(zu)增(zeng)(zeng)大或(huo)减小(xiao)。这(zhei)样的(de)(de)MOS场(chang)效(xiao)应晶体(ti)(ti)(ti)(ti)管(guan)(guan)称(cheng)为P沟(gou)道(dao)(dao)(dao)耗尽型场(chang)效(xiao)应晶体(ti)(ti)(ti)(ti)管(guan)(guan)。统称(cheng)为PMOS晶体(ti)(ti)(ti)(ti)管(guan)(guan)。

P沟(gou)道MOS晶体(ti)管(guan)的(de)空(kong)穴(xue)迁移率低,因而在MOS晶(jing)体(ti)(ti)管(guan)的(de)几何尺寸和工(gong)作(zuo)电(dian)(dian)(dian)(dian)压(ya)(ya)绝对值相等的(de)情(qing)况(kuang)下，PMOS晶(jing)体(ti)(ti)管(guan)的(de)跨(kua)导小(xiao)于N沟道(dao)MOS晶(jing)体(ti)(ti)管(guan)。此外，P沟道(dao)MOS晶(jing)体(ti)(ti)管(guan)阈值电(dian)(dian)(dian)(dian)压(ya)(ya)的(de)绝对值一般偏高，要(yao)求有较高的(de)工(gong)作(zuo)电(dian)(dian)(dian)(dian)压(ya)(ya)。它的(de)供电(dian)(dian)(dian)(dian)电(dian)(dian)(dian)(dian)源的(de)电(dian)(dian)(dian)(dian)压(ya)(ya)大(da)小(xiao)和极(ji)性,与(yu)双极(ji)型晶(jing)体(ti)(ti)管(guan)——晶(jing)体(ti)(ti)管(guan)逻(luo)辑(ji)电(dian)(dian)(dian)(dian)路(lu)(lu)(lu)不兼容。PMOS因逻(luo)辑(ji)摆幅大(da)，充电(dian)(dian)(dian)(dian)放电(dian)(dian)(dian)(dian)过程长(zhang)，加之器件(jian)跨(kua)导小(xiao)，所(suo)以工(gong)作(zuo)速度更低，在NMOS电(dian)(dian)(dian)(dian)路(lu)(lu)(lu)(见(jian)N沟道(dao)金属—氧(yang)化物(wu)—半导体(ti)(ti)集(ji)成电(dian)(dian)(dian)(dian)路(lu)(lu)(lu))出现之后(hou)，多数(shu)已(yi)为(wei)NMOS电(dian)(dian)(dian)(dian)路(lu)(lu)(lu)所(suo)取代。只是,因PMOS电(dian)(dian)(dian)(dian)路(lu)(lu)(lu)工(gong)艺简单(dan),价格(ge)便(bian)宜，有些中规模和小(xiao)规模数(shu)字控制电(dian)(dian)(dian)(dian)路(lu)(lu)(lu)仍采用PMOS电(dian)(dian)(dian)(dian)路(lu)(lu)(lu)技术。

PMOS集成电(dian)(dian)路(lu)是一种适合在(zai)低速(su)、低频领域内应用(yong)的器件。PMOS集成电(dian)(dian)路(lu)采用(yong)-24V电(dian)(dian)压供电(dian)(dian)。如(ru)图5所示的CMOS-PMOS接(jie)口(kou)(kou)电(dian)(dian)路(lu)采用(yong)两(liang)种电(dian)(dian)源供电(dian)(dian)。采用(yong)直接(jie)接(jie)口(kou)(kou)方式(shi)，一般CMOS的电(dian)(dian)源电(dian)(dian)压选择在(zai)10～12V就(jiu)能满(man)足PMOS对(dui)输入电(dian)(dian)平(ping)的要求(qiu)。

PMOS导通(tong)条件

P沟道mos管作(zuo)为开(kai)关，栅源(yuan)的阀值为-0.4V，当栅源(yuan)的电压差为-0.4V就会使DS导(dao)通，如果S为2.8V，G为1.8V，那(nei)么GS=-1V，mos管导(dao)通，D为2.8V

如(ru)果S为2.8V，G为2.8V，VGSw

那么mos管不导(dao)通，D为0V，

所以，如果(guo)2.8V连接到S，要mos管导通为(wei)系统供电，系统连接到D，利用(yong)G控制。

那么和G相(xiang)连的(de)GPIO高电平要(yao)2.8-0.4=2.4V以(yi)上，才能使mos管(guan)关断，低电平使mos管(guan)导通。

 如果控制G的(de)(de)GPIO的(de)(de)电压区域(yu)为(wei)1.8V，那么GPIO高电平的(de)(de)时候为(wei)1.8V，GS为(wei)1.8-2.8=-1V，mos管导通，不能够(gou)关断。

GPIO为(wei)低电平(ping)的时候，假(jia)如0.1V，那么GS为(wei)0.1-2.8=-2.7V,mos管导通。这(zhei)种情况下GPIO就不能够控制mos管的导通和关(guan)闭。 

当栅(zha)源的电压(ya)差为-0.4V就会使(shi)DS导通，如果S为5V，G为4V，那么GS=-1V，mos管导通，D为5V

PMOS管型(xing)(xing)号选型(xing)(xing)

联系方式：邹先生（mos管原厂家）

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