P沟道mosfet选型和参数(shu)资料及工(gong)作原理、工(gong)作特性详解-KIA MOS管
信(xin)息来源：本(ben)站(zhan) 日期：2018-09-11
金属氧(yang)化物半导(dao)体(ti)(ti)(ti)(ti)(ti)场(chang)(chang)效(xiao)应(ying)(MOS)晶体(ti)(ti)(ti)(ti)(ti)管可分为(wei)(wei)(wei)N沟道(dao)(dao)与P沟道(dao)(dao)两(liang)大类， P沟道(dao)(dao)硅MOS场(chang)(chang)效(xiao)应(ying)晶体(ti)(ti)(ti)(ti)(ti)管在N型(xing)硅衬底(di)上有(you)两(liang)个P+区，分别(bie)叫做源极和(he)漏(lou)极，两(liang)极之间(jian)不通导(dao)，柵极上加(jia)有(you)足够的(de)(de)(de)正(zheng)电(dian)压(ya)(源极接(jie)(jie)地)时(shi)，柵极下(xia)的(de)(de)(de)N型(xing)硅表(biao)面呈现P型(xing)反型(xing)层，成为(wei)(wei)(wei)衔(xian)接(jie)(jie)源极和(he)漏(lou)极的(de)(de)(de)沟道(dao)(dao)。改(gai)动栅压(ya)可以改(gai)动沟道(dao)(dao)中的(de)(de)(de)电(dian)子密度，从而改(gai)动沟道(dao)(dao)的(de)(de)(de)电(dian)阻。这种MOS场(chang)(chang)效(xiao)应(ying)晶体(ti)(ti)(ti)(ti)(ti)管称(cheng)为(wei)(wei)(wei)P沟道(dao)(dao)增(zeng)强型(xing)场(chang)(chang)效(xiao)应(ying)晶体(ti)(ti)(ti)(ti)(ti)管。假(jia)设N型(xing)硅衬底(di)表(biao)面不加(jia)栅压(ya)就已(yi)存在P型(xing)反型(xing)层沟道(dao)(dao)，加(jia)上恰当的(de)(de)(de)偏压(ya)，可使沟道(dao)(dao)的(de)(de)(de)电(dian)阻增(zeng)大或减(jian)小。这样(yang)的(de)(de)(de)MOS场(chang)(chang)效(xiao)应(ying)晶体(ti)(ti)(ti)(ti)(ti)管称(cheng)为(wei)(wei)(wei)P沟道(dao)(dao)耗尽型(xing)场(chang)(chang)效(xiao)应(ying)晶体(ti)(ti)(ti)(ti)(ti)管。统称(cheng)为(wei)(wei)(wei)PMOS晶体(ti)(ti)(ti)(ti)(ti)管。
P沟(gou)道mosfet的(de)(de)(de)空(kong)穴迁移(yi)率低，因(yin)而在MOS晶体(ti)管(guan)(guan)的(de)(de)(de)几何尺寸和(he)工作电(dian)(dian)(dian)压绝对值相等(deng)的(de)(de)(de)情况下，PMOS晶体(ti)管(guan)(guan)的(de)(de)(de)跨导(dao)(dao)小于N沟(gou)道mosfet。此外，P沟(gou)道mosfet阈值电(dian)(dian)(dian)压的(de)(de)(de)绝对值普(pu)通(tong)偏高(gao)(gao)，恳求(qiu)有较(jiao)高(gao)(gao)的(de)(de)(de)工作电(dian)(dian)(dian)压。它(ta)的(de)(de)(de)供电(dian)(dian)(dian)电(dian)(dian)(dian)源的(de)(de)(de)电(dian)(dian)(dian)压大(da)小和(he)极(ji)性，与(yu)双极(ji)型(xing)晶体(ti)管(guan)(guan)——晶体(ti)管(guan)(guan)逻(luo)辑电(dian)(dian)(dian)路不兼容。P沟(gou)道mosfet因(yin)逻(luo)辑摆幅大(da)，充电(dian)(dian)(dian)放(fang)电(dian)(dian)(dian)过程长，加(jia)之(zhi)器件跨导(dao)(dao)小，所(suo)以工作速度更低，在NMOS电(dian)(dian)(dian)路(见(jian)N沟(gou)道金属—氧化(hua)物—半导(dao)(dao)体(ti)集成电(dian)(dian)(dian)路)呈现之(zhi)后，多数(shu)(shu)已为NMOS电(dian)(dian)(dian)路所(suo)取代。只(zhi)是，因(yin)PMOS电(dian)(dian)(dian)路工艺简(jian)单(dan)，价(jia)钱(qian)低价(jia)，有些中范围(wei)和(he)小范围(wei)数(shu)(shu)字控制电(dian)(dian)(dian)路仍采用PMOS电(dian)(dian)(dian)路技术。PMOS的(de)(de)(de)特性，Vgs小于一定的(de)(de)(de)值就会(hui)导(dao)(dao)通(tong)，适宜(yi)用于源极(ji)接VCC时的(de)(de)(de)情况（高(gao)(gao)端驱动(dong)）。但是，固然PMOS可(ke)以很便当地用作高(gao)(gao)端驱动(dong)，但由于导(dao)(dao)通(tong)电(dian)(dian)(dian)阻大(da)，价(jia)钱(qian)贵，交流种类少等(deng)缘由，在高(gao)(gao)端驱动(dong)中，通(tong)常还是运用NMOS。
正常工作时，P沟(gou)道增强型MOS管(guan)的衬(chen)底(di)必需(xu)与源(yuan)极(ji)相连，而漏心(xin)极(ji)的电压Vds应为(wei)负值，以(yi)保证两个P区(qu)与衬(chen)底(di)之间的PN结均为(wei)反偏(pian)，同时为(wei)了在衬(chen)底(di)顶表(biao)面左近(jin)构成导(dao)电沟(gou)道，栅极(ji)对源(yuan)极(ji)的电压Vgs也应为(wei)负。
1．Ｖds≠Ｏ的情况导电(dian)沟道(dao)构成以后，ＤＳ间(jian)加(jia)负向电(dian)压时(shi)，那么在源(yuan)极(ji)(ji)(ji)与漏(lou)极(ji)(ji)(ji)之间(jian)将有漏(lou)极(ji)(ji)(ji)电(dian)流Ｉd流通(tong)，而(er)且Ｉd随Vds而(er)增加(jia)．Ｉd沿沟道(dao)产生的压降使(shi)沟道(dao)上各点与栅极(ji)(ji)(ji)间(jian)的电(dian)压不再相(xiang)等，该电(dian)压削(xue)弱(ruo)了栅极(ji)(ji)(ji)中负电(dian)荷电(dian)场(chang)的作用，使(shi)沟道(dao)从漏(lou)极(ji)(ji)(ji)到源(yuan)极(ji)(ji)(ji)逐渐变窄．当(dang)Ｖds增大到使(shi)Ｖgd＝Ｖgs（TH），沟道(dao)在漏(lou)极(ji)(ji)(ji)左(zuo)近呈现(xian)预夹断．
2．导(dao)电(dian)沟道的(de)(de)构(gou)成（Ｖds＝0）当Vds=0时(shi)，在(zai)栅(zha)源(yuan)之间加负电(dian)压Vgs，由于绝缘(yuan)层(ceng)(ceng)(ceng)的(de)(de)存在(zai)，故没有电(dian)流(liu)，但是金属栅(zha)极(ji)(ji)被(bei)补充电(dian)而聚集负电(dian)荷，Ｎ型(xing)半导(dao)体中的(de)(de)多子(zi)电(dian)子(zi)被(bei)负电(dian)荷排(pai)斥向(xiang)体内运动，表面留下带正(zheng)电(dian)的(de)(de)离子(zi)，构(gou)成耗尽(jin)层(ceng)(ceng)(ceng)，随着Ｇ、Ｓ间负电(dian)压的(de)(de)增加，耗尽(jin)层(ceng)(ceng)(ceng)加宽(kuan)，当Vgs增大到一定值时(shi)，衬(chen)底中的(de)(de)空(kong)穴（少子(zi)）被(bei)栅(zha)极(ji)(ji)中的(de)(de)负电(dian)荷吸收到表面，在(zai)耗尽(jin)层(ceng)(ceng)(ceng)和绝缘(yuan)层(ceng)(ceng)(ceng)之间构(gou)成一个Ｐ型(xing)薄(bo)层(ceng)(ceng)(ceng)，称反(fan)型(xing)层(ceng)(ceng)(ceng)，这个反(fan)型(xing)层(ceng)(ceng)(ceng)就构(gou)成漏源(yuan)之间的(de)(de)导(dao)电(dian)沟道，这时(shi)的(de)(de)Ｖgs称为开启电(dian)压Vgs（th），Vgs到Vgs（th）后再增加，衬(chen)底表面感(gan)应的(de)(de)空(kong)穴越多，反(fan)型(xing)层(ceng)(ceng)(ceng)加宽(kuan)，而耗尽(jin)层(ceng)(ceng)(ceng)的(de)(de)宽(kuan)度(du)却不再变化，这样我们可以(yi)用Vgs的(de)(de)大小控制导(dao)电(dian)沟道的(de)(de)宽(kuan)度(du)。
p沟道mosfet作为开(kai)关使用(yong)时，是由(you)Vgs的电压值来控(kong)制S（source源极）和 D（drain漏极）间的通(tong)断。
Vgs的最小(xiao)阀(fa)值电压(ya)为：0.4v，也就是说当 S（source源极(ji)）电压(ya) — G（gate栅极(ji)）极(ji) > 0.4V 时(shi)， 源极(ji) 和 漏极(ji)导通。
并且Vs = Vd ，S极(ji)电(dian)(dian)压等于(yu)D极(ji)电(dian)(dian)压。
例(li)如：S极 为 3.3V，G极 为0.1V，则 Vgs = Vg — Vs = -3.2 pmos管导通，D极电压为3.3V
一般(ban)pmos管当(dang)做开关(guan)使用的时，S极(ji)和D极(ji)之间几乎没有压降。
在实际使(shi)用(yong)中(zhong)，一般(ban)G极接(jie)MCU控制管(guan)脚，S极接(jie)电源正极VCC，D极接(jie)器件(jian)的输入(ru)。实际使(shi)用(yong)中(zhong)的一个样例如下(xia)：
RF_CTRL为(wei)低电平的时候(hou)，RF_RXD 和 RF_TXD上的电压为(wei)VDD。
下面电(dian)路(lu)为(wei)P沟道MOS管用作电(dian)路(lu)切换开关使用电(dian)路(lu)：
电路分(fen)析如下：
pmos的(de)(de)(de)开(kai)启条件是(shi)VGS电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)为(wei)(wei)负(fu)压(ya)(ya)(ya)(ya)，并且电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)的(de)(de)(de)绝对值大(da)于最低开(kai)启电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)，一般小(xiao)(xiao)功率的(de)(de)(de)PMOS管(guan)(guan)(guan)的(de)(de)(de)最小(xiao)(xiao)开(kai)启电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)为(wei)(wei)0.7V左(zuo)右，假(jia)设(she)电(dian)(dian)(dian)(dian)池(chi)充(chong)满电(dian)(dian)(dian)(dian)，电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)为(wei)(wei)4.2V,VGS=-4.2V，PMOS是(shi)导(dao)(dao)通的(de)(de)(de)，电(dian)(dian)(dian)(dian)路是(shi)没有(you)问(wen)(wen)题(ti)的(de)(de)(de)。当5V电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)时(shi)，G极(ji)(ji)的(de)(de)(de)电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)为(wei)(wei)5V，S极(ji)(ji)的(de)(de)(de)电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)为(wei)(wei)5VV-二(er)极(ji)(ji)管(guan)(guan)(guan)压(ya)(ya)(ya)(ya)降(jiang)(jiang)（0.5左(zuo)右）=4.5V，PMOS管(guan)(guan)(guan)关(guan)段，当没有(you)5V电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)时(shi)，G极(ji)(ji)电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)下拉为(wei)(wei)0V，S极(ji)(ji)的(de)(de)(de)电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)为(wei)(wei)电(dian)(dian)(dian)(dian)池(chi)电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)（假(jia)设(she)电(dian)(dian)(dian)(dian)池(chi)充(chong)满电(dian)(dian)(dian)(dian)4.2V）-MOS管(guan)(guan)(guan)未导(dao)(dao)通二(er)极(ji)(ji)管(guan)(guan)(guan)压(ya)(ya)(ya)(ya)降(jiang)(jiang)（0.5V）=3.7，这(zhei)样PMOS就导(dao)(dao)通，二(er)极(ji)(ji)管(guan)(guan)(guan)压(ya)(ya)(ya)(ya)降(jiang)(jiang)就没有(you)了这(zhei)样VGS=-4.2V.PMOS管(guan)(guan)(guan)导(dao)(dao)通对负(fu)载供电(dian)(dian)(dian)(dian)。在这(zhei)里用(yong)(yong)一个(ge)肖特(te)基二(er)极(ji)(ji)管(guan)(guan)(guan)（SS12）也可(ke)以解(jie)决这(zhei)个(ge)问(wen)(wen)题(ti)，不(bu)(bu)过(guo)就是(shi)有(you)0.3V左(zuo)右的(de)(de)(de)电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)降(jiang)(jiang)。这(zhei)里使(shi)用(yong)(yong)PMOS管(guan)(guan)(guan)，PMOS管(guan)(guan)(guan)完全(quan)导(dao)(dao)通，内阻(zu)(zu)比较小(xiao)(xiao)，优(you)与(yu)肖特(te)基，几乎没有(you)压(ya)(ya)(ya)(ya)降(jiang)(jiang)。不(bu)(bu)过(guo)下拉电(dian)(dian)(dian)(dian)阻(zu)(zu)使(shi)用(yong)(yong)的(de)(de)(de)有(you)点(dian)大(da)，驱动PMOS不(bu)(bu)需要电(dian)(dian)(dian)(dian)流的(de)(de)(de)，只要电(dian)(dian)(dian)(dian)压(ya)(ya)(ya)(ya)达到就可(ke)以了，可(ke)以使(shi)用(yong)(yong)大(da)电(dian)(dian)(dian)(dian)阻(zu)(zu)，减少工(gong)作(zuo)电(dian)(dian)(dian)(dian)流，推荐(jian)使(shi)用(yong)(yong)10K-100K左(zuo)右的(de)(de)(de)电(dian)(dian)(dian)(dian)阻(zu)(zu)。
深圳市利盈娱乐半导体(ti)(ti)科技(ji)有限公(gong)司.是一(yi)家专业从事(shi)中、大(da)、功率(lv)场(chang)效应(ying)管(guan)(guan)(MOSFET)、快速恢复二极(ji)管(guan)(guan)、三端稳压管(guan)(guan)开发设计，集研发、生产和销售为一(yi)体(ti)(ti)的国家高新技(ji)术(shu)企业。这里主要是讲(jiang)述P沟道(dao)mosfet的参(can)数、型号。
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