CMOS的输入输出特性

在(zai)讨论与其他器件衔接传(chuan)输(shu)(shu)(shu)信(xin)号(hao)的接口问题(ti)之前，首先需求深化了解本(ben)身的输(shu)(shu)(shu)入(ru)、输(shu)(shu)(shu)出特(te)性。还需认识(shi)在(zai)信(xin)号(hao)传(chuan)输(shu)(shu)(shu)过程中(zhong)的延迟时间(jian)、噪(zao)声特(te)性等问题(ti)。

1．输入特性

图(tu)13.3示出CMOS器件(jian)的输(shu)入等效(xiao)电(dian)(dian)路(lu)（以(yi)(yi)F写作输(shu)入电(dian)(dian)路(lu)）以(yi)(yi)及输(shu)入电(dian)(dian)流(liu)—输(shu)入电(dian)(dian)压(ya)特性。CMOS的输(shu)入端(duan)附加有防(fang)静电(dian)(dian)和外来浪涌进入输(shu)入栅极的维(wei)护电(dian)(dian)路(lu)。CMOS的输(shu)入栅极电(dian)(dian)阻是几(ji)十MQ以(yi)(yi)上的高电(dian)(dian)阻（高阻抗(kang)），所(suo)以(yi)(yi)实践(jian)的输(shu)入特性看(kan)到的是维(wei)护电(dian)(dian)路(lu)的特性。CMOS输(shu)入电(dian)(dian)路(lu)（维(wei)护电(dian)(dian)路(lu)）可分为以(yi)(yi)下四(si)品种型：

(1)串联(lian)电(dian)阻+上拉二极管(PU)&下拉二极管(PD)。

 (2) PU＆PD(扩散(san)电(dian)阻型(xing)PU＆PD，扩散(san)电(dian)阻型(xing)PD&PU)。

 (3)扩散电(dian)阻(zu)型，二极管+PU/PD(扩散电(dian)阻(zu)型PU+PD，扩散电(dian)阻(zu)型PD+PU)。

(4)只要PD(PD或者(zhe)扩散电(dian)阻(zu)型PD)。

不管哪品种型，输(shu)入电(dian)压在GND-1VDD之间(jian)，从输(shu)入到(dao)VDD或者到(dao)GND之间(jian)都具有几十MΩ以上的高电(dian)阻(zu)（高阻(zu)抗）。

具有PU的(de)(de)(de)电(dian)(dian)(dian)(dian)路中(zhong)，假(jia)(jia)如输入(ru)(ru)电(dian)(dian)(dian)(dian)压(ya)超越VDD+VF(二极(ji)(ji)管(guan)的(de)(de)(de)正向(xiang)(xiang)电(dian)(dian)(dian)(dian)压(ya)降：0.6～0.8V)，那么(me)(me)电(dian)(dian)(dian)(dian)流(liu)将从(cong)输入(ru)(ru)向(xiang)(xiang)VDD活(huo)动；假(jia)(jia)如输入(ru)(ru)电(dian)(dian)(dian)(dian)压(ya)低(di)于GND-VF(0.6-0.8V)，那么(me)(me)电(dian)(dian)(dian)(dian)流(liu)将从(cong)GND向(xiang)(xiang)输人活(huo)动。当(dang)二极(ji)(ji)管(guan)输入(ru)(ru)端有维护(hu)电(dian)(dian)(dian)(dian)阻时，流(liu)过二极(ji)(ji)管(guan)的(de)(de)(de)电(dian)(dian)(dian)(dian)流(liu)值(zhi)被电(dian)(dian)(dian)(dian)阻限制。在没有PU只要PD的(de)(de)(de)维护(hu)电(dian)(dian)(dian)(dian)路（电(dian)(dian)(dian)(dian)压(ya)变换(huan)功用：高(gao)电(dian)(dian)(dian)(dian)压(ya)变换(huan)为低(di)电(dian)(dian)(dian)(dian)压(ya)）中(zhong)，电(dian)(dian)(dian)(dian)流(liu)与(yu)VDD的(de)(de)(de)值(zhi)无关，到达PD的(de)(de)(de)击穿电(dian)(dian)(dian)(dian)压(ya)时开(kai)端活(huo)动。

没有串(chuan)联(lian)电(dian)(dian)阻(zu)或扩散电(dian)(dian)阻(zu)的电(dian)(dian)流(liu)(liu)途径中，当(dang)电(dian)(dian)流(liu)(liu)开端流(liu)(liu)过二极管时，瞬(shun)时大(da)电(dian)(dian)流(liu)(liu)会超越最大(da)额(e)定电(dian)(dian)流(liu)(liu)，招致器(qi)件被击穿或劣化(hua)，所以要(yao)惹起留意。

2．输出特性

图13.4示出CMOS器件的输出等效电路。输出电压在GND～VDD之间表现出通常的MOS晶体管的输出特性。这种状态下，具有由输出电流一输出电压计算出的输出阻抗特性（规范逻辑中是几十Ω）。

在CMOS器件的(de)输(shu)出级(ji)，由于(yu)存在输(shu)出晶体(ti)管的(de)寄生二极管，所(suo)以假如加GND以下或者VDD以上的(de)输(shu)出电(dian)压，会(hui)有(you)超(chao)越最大(da)额定值的(de)正向电(dian)流流过(guo)寄生二极管，招致器件劣化以至(zhi)被击穿，必需留(liu)意这一点(dian)。

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